The present invention relates to a DC-DC converter, and more particularly, to a circuit and method for controlling a DC-DC converter.
A portable electronic device, such as a notebook type personal computer and a gaming device, is provided with a plurality of semiconductor integrated circuit devices and a battery for supplying operational power to the plurality of semiconductor integrated circuit devices. Since the output voltage decreases as the battery discharges, a DC-DC converter is used to keep the operational power voltage constant.
FIG. 1 is a schematic circuit diagram showing a first example of a voltage control DC-DC converter 1 in the prior art. The DC-DC converter 1 includes a control circuit 2, a choke coil L1, a smoothing capacitor C1, and a discharge resistor BR.
The control circuit 2 receives input voltage Vi as power supply voltage Vcc. The control circuit 2 also receives output voltage Vo as a feedback signal FB of the DC-DC converter 1. The control circuit 2 includes a power supply circuit 3, an error amplifier 4, a PWM comparator 5, a triangular wave oscillator 6, a drive circuit (DRVH) 7, a drive circuit (DRVL) 8, output transistors T1 and T2, and resistors R1 and R2. The power supply circuit 3 generates internal power from the power supply voltage Vcc and supplies the internal power to the error amplifier 4, the PWM comparator 5, and the triangular wave oscillator 6.
The error amplifier 4 of the control circuit 2 amplifies differential voltage between voltage, which is obtained by dividing the feedback signal FB with the resistors R1 and R2, and voltage of a reference power supply e1 to provide an amplified error signal to a non-inverting input terminal of the PWM comparator 5. The reference power supply e1 is set such that its voltage is substantially equal to the divided voltage generated by the resistors R1 and R2 when the output voltage Vo reaches a specified value.
The triangular wave oscillator 6 provides a triangular wave signal having a constant frequency to an inverting input terminal of the PWM comparator 5. The PWM comparator 5 generates an output signal QH at a high (H) level and an output signal QL at a low (L) level when the input voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal. The PWM comparator 5 generates the output signal QH at an L level and the output signal QL at an H level when the input voltage at the non-inverting input terminal is lower than the voltage at the inverting input terminal.
The drive circuit (DRVH) 7 converts the level of the output signal QH of the PWM comparator 5 to generate a control signal DH and provides the control signal DH to the gate of the output transistor T1. The drive circuit (DRVL) 8 converts the level of the output signal QL of the PWM comparator 5 to generate a control signal DL and provides the control signal DL to the gate of the output transistor T2. The output transistor T1 is a P-channel MOS transistor having a source receiving a first power supply voltage Vcc. The output transistor T2 is an N-channel MOS transistor having a source connected to a low-potential power supply (ground). The output transistor T1 is activated in response to an L level control signal DH. The output transistor T2 is activated in response to an H level control signal DL.
In the voltage control DC-DC converter 1, the output transistor T1 is activated in fixed cycles in accordance with the triangular wave signal from the triangular wave oscillator 6. The activation of the output transistor T1 increases the output voltage Vo, and the output voltage Vo is smoothed by the smoothing capacitor C1. When the output transistor T1 is inactivated, energy stored in the choke coil L1 is discharged. As the energy in the choke coil L1 decreases, the output voltage Vo decreases. When the divided voltage generated by the resistors R1 and R2 becomes lower than the voltage of the reference power supply e1, the output transistor T1 is activated.
An increase in the output voltage Vo decreases the output voltage of the error amplifier 4 and the activation time of the output transistor T1. A decrease in the output voltage Vo increases the output voltage of the error amplifier 4 and lengthens the activation time of the output transistor T1. Such operations keep the output voltage Vo fixed based on the reference power supply e1.
The smoothing capacitor C1 is connected in parallel to the discharge resistor BR to protect the control circuit 2 when the input voltage Vi is interrupted. More specifically, if the current consumption of a load is extremely low or if there is no load on the DC-DC converter 1, the output voltage Vo of the DC-DC converter 1 is kept at a relatively high value for a long period of time by the electric charge stored in the smoothing capacitor C1. In this state, the error amplifier 4 is not supplied with operational power from the power supply circuit 3 due to the interruption of the input voltage Vi. Therefore, voltage higher than the voltage at the power supply terminal is supplied to the input terminal of the error amplifier 4. This may cause a deficiency, such as a latch-up or a burnout, in the error amplifier 4. In order to prevent such a deficiency, the electric charge stored in the smoothing capacitor C1 is discharged via the discharge resistor BR. This readily decreases the output voltage Vo of the DC-DC converter 1 to 0 V.
However, the discharge resistor BR is constantly supplied with current. This lowers the efficiency of the DC-DC converter 1. To avoid this problem, Japanese Patent Laid-Open Publication No. 5-30755 describes a method in which a switch device is connected in series to a discharge resistor RB, and the switch device is activated only when electric charge is discharged from a capacitor. This method, however, requires the switch device and a drive circuit for driving the switch device in addition to the discharge resistor.
FIG. 2 is a schematic block diagram showing a second example of a DC-DC converter 10 in the prior art.
The DC-DC converter 10 includes a control circuit 11, a choke coil L1, a smoothing capacitor C1, and a soft-start capacitor C2. The soft-start capacitor C2 is connected to an inverting input terminal of an error amplifier 4a. The soft-start capacitor C2 is also connected to a constant current source 12 or a resistor R3 via a switch SW of the control circuit 11. When powered on, the control circuit 11 controls the switch SW so that the soft-start capacitor C2 is connected to the constant current source 12. This stores electric charge in the soft-start capacitor C2 in accordance with the current supplied from the constant current source 12. The storage of the electric charge increases the voltage of a soft-start signal SS. When the voltage of the soft-start signal SS is lower than the voltage of a reference power supply e1, the output voltage Vo of the DC-DC converter 10 increases at the same rate as the increase rate of the voltage of the soft-start signal SS. When the voltage of the soft-start signal SS becomes higher than the voltage of the reference power supply e1, the error amplifier 4a amplifies the difference between the voltage of the reference power supply e1 and the output voltage Vo of the DC-DC converter 10. Thus, the output voltage Vo of the DC-DC converter 10 is controlled by the reference power supply e1. In this manner, the gradient of the output voltage during activation of the DC-DC converter 10 is controlled by the voltage of the soft-start signal SS (i.e., the voltage of the capacitor C2) and does not depend on the load of the DC-DC converter 10.
When the DC-DC converter 10 stops operating, the capacitor C2 is connected to the resistor R3 via the switch SW. Accordingly, the electric charge of the capacitor C2 is discharged via the resistor R3. This gradually decreases the voltage of the soft-start signal SS and gradually decreases the output voltage Vo of the DC-DC converter 10. Thus, when the DC-DC converter 10 stops operating, the gradient of the output voltage is controlled by the voltage of the soft-start signal SS (i.e., the voltage of the capacitor C2) and does not depend on the load of the DC-DC converter 10.
Therefore, the DC-DC converter 10 is capable of gradually decreasing the output voltage Vo without depending on the load and without using a discharge resistor or switch device. Japanese Patent Laid-Open Publication Nos. 9-154275 and 10-323026 describe configurations similar to the DC-DC converter of the second prior art example.